1. Field of the Invention
The present invention relates to an arithmetic circuit for concatenated codes and an address control method, and particularly to an arithmetic circuit for concatenated codes in which an efficient circuit structure is realized and an algorithm of improved concatenated codes is applied, and an address control method.
2. Description of the Related Art
In recent years, telecommunications carriers in all the world are configuring a next generation network (hereinafter referred to as NGN). A transmission network in the NGN has a hierarchical structure as shown in FIG. 1, and in this structure, an optical core metro network of from metro/access network (100 Km or less) to core (exceeding 1000 Km) is configured by an optical transport system.
In the optical transport system, in order to reduce the maintenance of a network administrator and the operation cost, Optical Transport Network (OTN) standards determined in Recommendation G.709 by International Telecommunication Union (Hereinafter referred to as ITU-T) in 2003 are adopted.
In the OTN standards, it is normally determined to add a function to correct an error applied to an information transmission frame by information deterioration on a transmission path, and Recommendation G.975.1 describes eight types of algorithms to realize the error correction function. Most of these are concatenated codes in which Bose-Chaudhuri-Hocquenghem (BCH) codes or Reed-solomon (RS) codes, which are basic in code logic, are combined.
Although the concatenated codes can realize a high coding gain, an enormous memory capacity is required. This is because the concatenated codes are based on the concept of rearrangement (interleaving) of data described later.
Circuits for performing error correction include a coding circuit and a decoding circuit. The coding circuit is a circuit to calculate a check code and adds it to a signal. The decoding circuit is a circuit to calculate a position, on a signal, of an error mixed on a transmission path and to return it to original data.
In general, when the coding/decoding circuit is mounted in an LSI, a memory is also usually mounted in the same chip. Such a memory is called an ON-CHIP memory. The memory in the LSI takes an area out of a logical circuit, consumes electric power and is liable to become the first cause of heat generation. Further, in a recent tendency, a diagnosis circuit is generally added to the memory, and this memory diagnosis circuit also becomes a problem as a non-negligible heat source.    [Non-patent document 1] ITU-T Recommendation G.709    [Non-patent document 2] ITU-T Recommendation G.975.1